1. Field of the Invention
The present invention relates generally to logic circuits and, more particularly, to a vector logic method and a dynamic mousetrap logic gate for implementing a self-timed monotonic logic progression with concise hardware requirements.
2. Related Art
Dynamic logic gates are used in the conventional design of logic circuits which require high performance and modest size. Dynamic logic gates require a periodic precharge to maintain and properly perform their intended logic function. In general, the precharge charges parasitic capacitances at a gate output node in order to sustain a logic state. However, once the precharge in the dynamic logic gate has been discharged, the gate can no longer perform another logic function until again precharged.
Examples of dynamic logic circuits are described in U.S. Pat. No. 5,015,882 to Houston et al. (domino logic), U.S. Pat. No. 4,899,066 to Aikawa et al., U.S. Pat. No. 4,841,174 to Chung et al., U.S. Pat. No. 4,827,160 to Okano, U.S. Pat. No. 4,730,266 to van Meerbergen et al., U.S. Pat. No. 4,700,086 to Ling et al., U.S. Pat. No. 4,692,637 to Shoji, U.S. Pat. No. 4,570,084 to Griffin et al., U.S. Pat. No. 4,569,032 to Lee, U.S. Pat. No. 4,468,575 to Mathes, and U.S. Pat. No. 4,352,031 to Holbrook et al.
Although meritorious to an extent, the use of conventional dynamic logic gates in logic networks has been limited historically because of associated design problems. Most dynamic logic gates suffer from functional incompleteness in that only non-inverting logic functions can be performed. An example of a dynamic logic family suffering from functional incompleteness is the well known domino logic. In this regard, see Weste, N. E., Principles Of CMOS VLSI Design, "CMOS Domino Logic," Section 5.525, p. 168, June 1988 and U.S. Pat. No. 5,015,882 to Houston et al. High performance adder logic circuits and multiplier logic circuits invariably require logic inversions in the critical logic path, as is well known in the art. Consequently, adder logic circuits and multiplier logic circuits are generally not built with conventional dynamic logic gates.
Furthermore, in many instances, conventional dynamic logic gates cannot be cascaded to perform combinational logic functions and still maintain their proper dynamic nature. Specifically, "static hazards," or "output skew," can arise. A static hazard is an inherent condition which occurs in combinational logic configurations as a result of propagation time delays. For example, consider a two-input exclusive-OR gate in a conventional binary logic system when both inputs are high and then both concurrently turn low. From a Boolean logic perspective, the output of the exclusive-OR gate should remain low before, during, and after the transition. However, in reality, one of the inputs will change just before the other. Consequently, the output of the exclusive-OR gate will undesirably and suddenly bounce high then low during the transition time. In a series of dynamic logic gates having an odd number of inversions in a logic path, static hazards will result in logic errors because the dynamic logic gates, once triggered, cannot further respond until again precharged.
U.S. Pat. No. 4,570,084 to Griffin et al. teaches a differential dynamic logic gate which is functionally complete and which does not exhibit static hazard problems. The Griffin gate practices well known binary decomposition in that it provides a pair of complementary outputs in response to complementary inputs. The Griffin gate has dual logic networks for receiving respectively an input and its complement. The dual logic networks are connected to respective dual inverters. Further, dual precharging mechanisms are disposed for precharging each input of the dual inverters.
The Griffin gate solves the static hazard problem by providing for a monotonic logic progression using binary decomposition with differential dynamic logic gates. A monotonic logic progression is the progression of logic evaluations on a logic path through a logic network wherein only the state transition from either low to high or high to low is considered on each logic path. In the Griffin gate, to implement a monotonic logic progression by considering only state transitions from low to high, complementary binary logic states are clocked from gate to gate. For every Q logic path, there is a complementary -Q logic path. Essentially, each logic path has been expanded into a two-rail path, one rail dedicated to propagating a logic low and one rail dedicated to propagating a logic high. Worth noting is that binary decomposition, and particularly, the dual-rail logic system, has been well known since the beginning of the computer era.
Another technique for achieving high performance in logic networks is to employ "self-timed" logic elements. Self-timed logic networks are considered very sophisticated in the art and are not completely understood by many designers. Thus, they have been implemented only to a very limited extent in logic networks. In a self-timed logic network, control of logic evaluations through the logic elements is delegated to the logic elements themselves, as opposed to a clock. Self-timed behavior is analogous to the scenario where an airplane does not depart until after all passengers scheduled for the flight have boarded the airplane. In self-timed systems, designers try to ensure that all system events occur in proper sequence, but nothing ever needs to occur at a particular time. For a further discussion of the concept of self-timing as well as the related valid and invalid states, refer to Weste and Eshraghian, Principles of CMOS VLSI Design, .sctn..sctn. 5.2.5-5.2.7, pp. 168-171, June 1988.
To date, no dynamic logic design has been developed which exhibits functional completeness, does not suffer from static hazards, and can employ self-timed elements in order to maximize performance.